๐Ÿ“Š Protocol View PCIe Protocol

PCIe Link Training & TLP Timing Diagram Generator

PCIe (PCI Express)

PCI Express is a high-speed serial interconnect standard for connecting processors to peripherals such as GPUs, SSDs, NICs, and FPGAs. It uses a layered architecture (Transaction, Data Link, Physical) with point-to-point differential lane pairs. Link widths scale as ร—1, ร—2, ร—4, ร—8, ร—16, and speeds have progressed from 2.5 GT/s (Gen1) to 32 GT/s (Gen5) and beyond.

๐Ÿ“Œ PCIe Key Features

  • Serial Point-to-Point: Differential TX/RX pairs per lane, scalable ร—1 to ร—16
  • Layered Architecture: Transaction Layer (TLPs) โ†’ Data Link Layer (DLLPs, CRC, retry) โ†’ Physical Layer (encoding, training)
  • LTSSM: Link Training and Status State Machine manages link bring-up, speed negotiation, power states, and error recovery
  • Generations: Gen1 (2.5 GT/s), Gen2 (5 GT/s), Gen3 (8 GT/s), Gen4 (16 GT/s), Gen5 (32 GT/s)
  • Encoding: 8b/10b (Gen1โ€“2), 128b/130b (Gen3+)
  • Power Management: L0s, L1, L2 low-power link states
  • Error Handling: CRC, ACK/NAK retry, ECRC, Advanced Error Reporting (AER)

๐Ÿ”„ PCIe LTSSM (Link Training and Status State Machine)

Detect.Quiet ยท Initial power-on state. Waiting to detect a receiver on the other end of the link.

๐Ÿ’ก Click state nodes to jump directly | Use buttons below to trigger events | ๐ŸŸจ Yellow = Current State

๐Ÿ”„ PCIe TLP Timing Waveform

๐Ÿ”ง JSON Editor

๐Ÿ“– LTSSM State Descriptions

1
Detect: Power-on entry point. The transmitter looks for a receiver by driving a common-mode voltage and checking for impedance change on the lane
2
Polling: Both sides exchange Training Sequences (TS1/TS2) to establish bit lock, symbol lock, and lane polarity
3
Configuration: Lanes are numbered and aggregated into a link; link width is negotiated
4
L0 (Active): Normal operating state โ€” TLPs and DLLPs flow across the link
5
Recovery: Re-training after errors, speed changes, or exit from low-power states; includes RcvrLock, Speed, RcvrCfg, and Idle substates
6
L0s / L1 / L2: Low-power link states with increasing entry/exit latency and power savings
7
Hot Reset / Disabled / Loopback: Special states for link reset, disable, or compliance testing

โšก PCIe Generations

Gen Transfer Rate Encoding Bandwidth ร—1 Bandwidth ร—16 Year
Gen1 2.5 GT/s 8b/10b 250 MB/s 4 GB/s 2003
Gen2 5 GT/s 8b/10b 500 MB/s 8 GB/s 2007
Gen3 8 GT/s 128b/130b ~984 MB/s ~15.8 GB/s 2010
Gen4 16 GT/s 128b/130b ~1969 MB/s ~31.5 GB/s 2017
Gen5 32 GT/s 128b/130b ~3938 MB/s ~63 GB/s 2019
Gen6 64 GT/s 1b/1b (PAM4) ~7877 MB/s ~126 GB/s 2022

๐Ÿ“ฆ PCIe Packet Types

Layer Packet Purpose Key Fields
Transaction TLP Data transfer (read, write, completion, config, message) Fmt, Type, Length, Requester/Completer ID, Address, Data
Data Link DLLP Link management (ACK/NAK, flow control, power mgmt) DLLP Type, Credits, CRC-16
Physical Ordered Sets Training (TS1/TS2), skip, compliance, EIEOS COM, TS identifier, lane/link numbers, speed

๐Ÿ†š PCIe vs Other Interconnects

๐Ÿš€ Bandwidth

PCIe Gen5 ร—16: 63 GB/s
CXL 3.0: 64 GB/s
USB4: 5 GB/s

๐Ÿ“ Topology

PCIe: Point-to-point
PCI: Shared bus
CXL: Point-to-point

๐Ÿ”Œ Lanes

PCIe: ร—1,ร—2,ร—4,ร—8,ร—16
USB4: ร—1,ร—2
Thunderbolt: ร—1

๐ŸŽฏ Use Case

GPU, NVMe SSD
Network cards
FPGA accelerators