📘 MIPI D-PHY Protocol Overview
⚡ Differential Signal Transmission
Uses differential pair transmission (Dp/Dn) with strong anti-interference capability, supports high-speed data transfer
Speed Range: 80Mbps - 2.5Gbps per lane
🔋 Dual-Mode Operation
LP Mode Low Power mode for control and low-speed data
HS Mode High Speed mode for bulk data transmission
🛣️ Multi-Lane Support
Supports 1-4 Data Lanes + 1 Clock Lane
Configurable lane count to balance speed and power consumption
📱 Mobile Application
Widely used in mobile phone cameras (CSI-2) and displays (DSI)
Supports MIPI CSI, DSI, UFS protocols
| Signal | Direction | Function |
|---|---|---|
| ClkP / ClkN | Input | Differential clock pair - DDR clock, provides sync clock in HS mode |
| D0p / D0n | Bidirectional | Data lane 0 differential pair - Transmits data and control information |
| D1p /D1n | Bidirectional | Data lane 1 differential pair (optional) |
| D2p / D2n | Bidirectional | Data lane 2 differential pair (optional) |
| D3p / D3n | Bidirectional | Data lane 3 differential pair (optional) |
🔄 MIPI D-PHY State Transitions
LP (Low Power) Mode States
LP-11 (Stop State)
│
├──> LP-10 ──> LP-00 ──> LP-01 (LP data transfer)
│ │ │ │
│ └─────────┴─────────┘
│
└─────┐
│ (Enter HS mode)
▼
LP-00 (HS-Request)
│
▼
LP-01 (HS-Prepare)
│
▼
HS-Zero → HS-Sync → HS-Data → HS-Trail
│
▼
LP-11 (Return to stop state)
HS (High Speed) Mode Timing
- HS-Request: Dp=0, Dn=0 (LP-00 state requests HS entry)
- HS-Prepare: Dp=0, Dn=1 (LP-01 state prepares differential transmission)
- HS-Zero: Differential signal establishes 0 state, ready for sync
- HS-Sync: Transmit sync sequence 0xB8
- HS-Data: Transmit actual data (DDR mode, sample on both clock edges)
- HS-Trail: Dp=0, Dn=1 ends transmission