📘 JTAG Protocol Overview
⚡ JTAG Core Features
- State Machine Driven: Controls 16-state TAP controller through TMS signal
- Boundary Scan: Test chip internal connections without physical contact
- Forced Reset: 5 consecutive TMS=1 returns to Test-Logic-Reset from any state
- 4-wire Interface: TCK, TMS, TDI, TDO (optional TRST reset line)
| Signal | Direction | Function |
|---|---|---|
| TCK | Input | Test Clock - Clock signal synchronizing all JTAG operations |
| TMS | Input | Test Mode Select - Key signal controlling TAP state machine transitions |
| TDI | Input | Test Data In - Serial data input to target device |
| TDO | Output | Test Data Out - Serial data output from target device |
| TRST | Input (Optional) | Test Reset - Asynchronously resets TAP controller to Test-Logic-Reset state |
🔄 TAP State Machine (16-State Finite State Machine)
Test-Logic-Reset Default reset; TAP idle. Five TMS=1 pulses return here from anywhere.
💡 Tip: 🟢 Green = TMS:0 | 🔴 Red = TMS:1 | 🟨 Yellow = Current State | Click state nodes to switch