📊 Protocol View I3C Protocol

Intelligent Timing Diagram Generation Tool

I3C (Improved Inter-Integrated Circuit)

I3C is the next-generation two-wire serial interface developed by MIPI Alliance. It maintains backward compatibility with I2C while offering significantly higher speeds, lower power consumption, and advanced features like In-Band Interrupts and Dynamic Addressing.

📌 I3C Key Features

  • Backward Compatible: Works with legacy I2C devices on the same bus
  • Much Faster: 12.5 MHz in SDR mode (vs I2C's 400 kHz-3.4 MHz), up to 25+ MHz in HDR modes
  • Lower Power: Push-pull signaling reduces power consumption compared to I2C's open-drain
  • In-Band Interrupts (IBI): Slaves can interrupt the master without dedicated interrupt pins
  • Dynamic Addressing: Auto-assign addresses during initialization (plus static addressing support)
  • Hot-Join: Devices can join the bus dynamically during operation
  • HDR Modes: High Data Rate modes (HDR-DDR, HDR-TSP, HDR-TSL) for ultra-high speed transfers

🔄 I3C vs I2C Comparison

Feature I2C I3C
Max Speed (Standard) 400 kHz - 3.4 MHz 12.5 MHz (SDR), 25+ MHz (HDR)
Signaling Open-drain only Push-pull (SDR) + Open-drain (I2C mode)
Interrupts Requires separate GPIO pins In-Band Interrupts (IBI) on bus
Addressing Static 7/10-bit Dynamic + Static addressing
Hot-Join Not supported Supported
Power Consumption Higher (pull-up power) Lower (push-pull efficiency)

🔄 I3C Timing Waveform (SDR Mode)

🔧 JSON Editor

📖 I3C SDR Mode Transmission Timing

1
START Condition: Similar to I2C - When SCL is high, SDA transitions from high to low
2
Address + R/W bit: 7-bit dynamic or static address + 1-bit read/write (0=write, 1=read)
3
ACK Response: Slave acknowledges by driving SDA low (T-bit in I3C terminology)
4
Data Transfer: 8-bit data, MSB first, using push-pull signaling for higher speed
5
T-bit (Transition bit): Receiver sends acknowledgment (similar to I2C ACK/NACK)
6
STOP Condition: When SCL is high, SDA transitions from low to high (or RESTART for continued transfer)

🚀 Advanced I3C Features

📡 In-Band Interrupts (IBI)

Slaves can request master attention by issuing an interrupt directly on the I3C bus, eliminating the need for separate interrupt pins. Master polls for pending IBIs or slaves can initiate them.

⚡ HDR Modes

HDR-DDR: Double Data Rate on both clock edges
HDR-TSP: Ternary Symbol Pure for maximum speed
HDR-TSL: Ternary Symbol Legacy for I2C compatibility

🔌 Hot-Join

Devices can dynamically join an active I3C bus by requesting dynamic address assignment from the master, enabling true plug-and-play functionality.

🏷️ Dynamic Addressing (ENTDAA)

Master automatically assigns unique 7-bit addresses to I3C devices during initialization using the ENTDAA (Enter Dynamic Address Assignment) command, based on device Provisional ID.